Integrated circuit (IC) chips are often electrically connected by wires (e.g., gold or aluminum wires) to a leadframe or a substrate in a packaging assembly to provide external signal exchange. Such wires are typically wire bonded to bond pads formed on an IC chip using thermal compression and/or ultrasonic vibration. A wire bonding process exerts thermal and mechanical stresses on a bond pad and on the underlying layers and structure below the bond pad. The bond pad structure needs to be able to sustain these stresses to ensure a good bonding of the wire.
During a wire bonding process and as the wire is pulled (after being bonded to the bond pad), this process also exerts large pulling or tension forces on the bond pad structure. These forces are translated downward into the intermetal dielectric (IMD) layers. If there is a weak point in the structure of the chip below the bond pad or near the bond pad that cannot withstand the pulling forces, peeling or delamination may occur. Recent innovations have strengthened the bond pad structures so that the bond pad structures can reliably endure the forces of wire bonding. However, now it has been found that certain interfaces in the IMD layers are becoming weak links causing peeling failure during wire bonding. In particular, it has been found that the interface between an etch stop layer and a copper line may be have insufficient adhesion strength (i.e., tensile strength), especially when copper oxide is formed on the copper line.
FIG. 1 is a simplified cross-section schematic of a prior art structure 20 showing copper lines 22 located below a bond pad (not shown). In FIG. 1, the two copper lines 22 shown are formed in an intermetal dielectric (IMD) layer 24. Typically, the insulating material of the IMD layer 24 is a low-k dielectric material (e.g., k<3.9). A barrier layer 28 is formed between the copper lines 22 and the surrounding dielectric materials, as is typical. Another IMD layer 30 is formed over the copper lines 22. An etch stop layer 32 is located between the upper IMD 30 and the copper lines 22. The etch stop layer 32 usually will have a stronger adhesion with the copper lines 22 than to a low-k dielectric material of the IMD layer 24.
As shown in FIG. 1, a copper oxide 34 is formed on the top surface of the copper lines 22. As noted above, the presence of the copper oxide 34 at this interface between the etch stop layer 32 and the copper lines 22 lessens the adhesion strength. Thus, it is preferable to remove the copper oxide 34 and/or prevent the formation of the copper oxide at this interface.
But in many current processes, the etch stop layer 32 is formed using an oxygen-containing precursor and/or the etch stop layer itself includes oxygen in its chemical structure (e.g., SiCO, Blok II by Applied Materials). In such cases, copper oxide 34 may develop at the interface between the etch stop layer 32 and the copper lines 22 during the formation of the etch stop layer 32, even if the copper 22 is precleaned prior the etch stop layer formation. Also, low-k dielectric materials for the IMD layer 30 are often formed using an O2 plasma and often these low-k dielectric materials include oxygen in their chemical structure. During the formation of an IMD layer 30 over an etch stop layer 32 and copper lines 22 (see e.g., FIG. 1), the oxygen may penetrate through the etch stop layer 32 and add to the formation of or cause the formation of copper oxide 34 on the copper lines 22. Thus, there is a need for a process and structure that will reduce or prevent the formation of a copper oxide 34 on the copper lines 22.